High performance sub-35 nm bulk CMOS with hybrid gate structures of NMOS ; Dopant Confinement Layer (DCL) / PMOS ; Ni-FUSI by using Flash Lamp Anneal (FLA) in Ni-silicidation

We applied Flash Lamp Annealing (FLA) in Ni-silicidation to our developed Dopant Confinement Layer (DCL) structure for the first time. DCL technique is a novel Stress Memorization Technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni Fully-silicide (Ni-FUSI) was selectively formed on gates, and both effective work function (WF) control and thinner Teff are improved. On the other hand, unlike pMOS, Ni-FUSI process is not performed in nMOS. Both higher activation of halo and reduction of parasitic resistance in nMOSFET are improved by the combination of DCL structure and FLA in Ni-silicidation. Consequently, the higher drive currents of 1255 μA/μm and 759 μA/μm were obtained I
off
=122 nA/μm and 112 nA/μm at |
Vdd
|=1.0 V for nMOSFET and pMOSFET, respectively.