Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL

We report TaC
_x
/HfSiON gate stack CMOS device with simplified gate 1
^st
process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaC
_x
composition, fixed charge free TaC
_x
/HfSiON device is successfully fabricated. Also, we have demonstrated that the strain effect in deeply scaled devices can be enhanced by eliminating the fixed charges in HfSiON, for the first time. Utilizing Stress Memorization Technique (SMT) and strained Contact Etch Stop Layer (CESL), L
_g
= 35 nm high performance TaC
_x
/HfSiON devices is achieved.