PVT-variations and supply-noise tolerant 45nm dense cache arrays with Diffusion-Notch-Free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits

PVT-tolerant and supply noise tracking word-line under-drive circuit, PMOS pass device, and dynamic voltage collapse enable read and write stable Diffusion-Notch-Free (DNF) 6T SRAM cells. Measurements from a 45-nm test-chip show 26X reduction in number of single bit failures using those schemes.