VLSI implementation of Inverse Discrete Wavelet Transform for JPEG 2000

This paper presents hardware design flow of the inverse discrete wavelet transform (IDWT) core which is the second-most computationally intensive block in JPEG 2000 image compression standard. Lifting scheme (LS) is implemented in designing the IDWT hardwire module that reduces the number of execution steps involved in computation to almost one-half of those needed with a conventional convolution approach. In addition, the LS is amenable to ldquoin-placerdquo computation, so that the IDWT can be implemented in low memory systems. The IDWT module does not comprise any hardware multiplier unit and therefore suitable for development of high performance image processor. The IDWT module has been developed in VHDL using Quartus II from Altera. The VHDL model is validated through simulation using ModelSim-Altera. Simulation results show the IDWT module can perform three levels inverse transform on a 256times256 forward transformed image in 8.7 ms. Latency of the system is calculated 50 ns and the power dissipation by the device is 662 mW. The IDWT module consumes just 57 combinational ALUTs and 60 logic registers of a Stratix II device, and runs at 300 MHz clock frequency, reaches a speed performance suitable for several real-time applications. Throughput in terms of input coefficients processed per second of the IDWT core is 7.13Msamples. The motivation in designing is to reduce its complexity, enhance its performance and to make it suitable development on a reconfigurable FPGA based platform for VLSI implementation.