4H-SiC MIS Capacitors and MISFETs With Deposited $\hbox{SiN}_{x}/ \hbox{SiO}_{2}$ Stack-Gate Structures

SiN
_x
/ SiO
₂
stack-gate structures, followed by N
₂
O annealing, have been investigated to improve the 4H-SiC metal- insulator-semiconductor (MIS) interface quality. Capacitance- voltage measurements on fabricated stack-gate MIS capacitors have indicated that the interface trap density is reduced by post- deposition annealing in N
₂
O at 1300degC. When the MIS capacitor with a SiN
_x
/ SiO
₂
thickness of 10 nm/50 nm was annealed in N
₂
O for 2 h, the interface trap density at E
_c
- 0.2 eV is below 1 X 10
¹¹
cm
^-2
eV
^-1
. Oxidation of SiN
_x
during N
₂
O annealing has resulted in the improvement of SiC MIS interface characteristics, as well as dielectric properties. The fabricated MISFETs with SiN
_x
/ SiO
₂
stack-gate structure annealed in N
₂
O demonstrate a reasonably high channel mobility of 32 cm
²
/ V ldr s on the (0001)Si face and 40 cm
²
/ V ldrs on the (0001) C face.