Recent status on Nano CMOS and future direction

Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is still questionable if we can successfully introduce sub-10 nm CMOS LSIs into market, because the problems expected at this moment — such as I
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ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. Considering the above situation, we formed a leading research group for future ultra-low power Nano-CMOS technology in 2003 – 2006, by the Special Coordination Funds for Promoting Science and Technology sponsored by Ministry of Education, Culture, Sports, Science and Technology, Japan, in order to conduct Nano-CMOS studies in advance to provide possible solutions to the future expected problems. The conclusion obtained by the group study was that, in the Nano-CMOS era, aggressive introduction of new materials, processes, structures, and operation concepts is required to solve the problems. Also, new physical analysis technique and physical model in order to predict and explain the atomic scale phenomena and properties at the new material interfaces are important. Unfortunately, there are no candidates among the so-called ‘beyond CMOS’ new devices, which are believed to really replace CMOS transistors usable for the products of highly integrated circuits within 20 years. Thus, our opinion is that we need to still continue CMOS based transistors — CMOS with FinFET, Nanowire FET, and even CNTFET — with ‘More Moore’ approach with combining that of ‘More than Moore.’