State boundedness of a discrete-time single-bit sigma-delta analog-to-digital converter

This paper focuses on the state boundedness issue of a single-bit sigma-delta analog-to-digital converter from circuit designers’ point of view. A discrete-time model has been studied. A design procedure which guarantees the state boundedness under given input magnitude and complying with given design specification is provided. In addition, an estimation of state bound is given. Although noise shaping is not the focus of this paper, the proposed design procedure gives circuit designers plenty of freedom to improve signal to noise ratio of the converter by using different loop filters and digital-to-analog converters, without sacrificing the desired state boundedness.