Process variability-induced timing failures— A challenge in nanometer CMOS low-power design

This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing—a delay overlapping stage (DOS) chart. We propose a circuit design optimization and verification methodology that considers process variability.