Improvement of power supply rejection ratio of LDO deteriorated by reducing power consumption

In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the conventional circuit. It is confirmed that about 40[dB] at 10[Hz] frequency and 20[dB] at 1[kHz] frequency of PSRR are together improved.