Efficient loop filter design in FPGAs for Phase Lock Loops in high-datarate wireless receivers — theory and case study

In most contemporary phase lock loops (PLLs) used in high-datarate wireless receivers, some or all of the PLL 's components are implemented digitally, in particular the PLL's loop filter. In this paper we develop the theory behind new efficient structures for the implementation of loop filters within FPGAs (field programmable gate arrays) using fixed-point arithmetic. The theory is then investigated via a case study, in which we present FPGA hardware mapping results which show that employing the proposed method results in a decrease of more than 70% in the logic gate count needed as compared to the conventional implementation.