Model based analysis of electrical and wear-out characteristics of 7 nm thin Ta2O5/SiOxNy stacks on Si

In this work 7 nm thin Ta
₂
O
₅
/SiO
_x
N
_y
insulating stacks on Si were studied by a combination of C-V If and leakage current (I-V) measurements, based on the comprehensive model involving different conduction mechanisms in Ta
₂
O
₅
and the interfacial SiO
_x
N
_y
layer. Equivalent oxide thickness (EOT) was determined using the extrapolation method for leaky high-k dielectrics proposed by Kar. Interface state densities were determined from the hf C-V characteristics by a standard method. Degradation after constant current stress (10 mA/cm
²
, 100 s) was analyzed in terms of oxide charge build-up, interface states density (D
_it
) generation and consumption of the interfacial layer. No significant variation of D
_it
with the stress was observed - midgap values (D
_itm
) for both fresh and stressed samples are close to 5times10
¹²
eV
^-1
cm
^-2
. The observed decrease in interface charge (QA is very small and could be attributed to the interfacial layer consumption. Fixed positive oxide charge increases for a small but significant amount of 4times10
¹¹
cm
^-2
. The most important variation with the stress is observed in the effective interfacial layer thickness (d
_IL
); it decreased for 0.12 nm as a result of the stress, leading to a decrease ofthe EOT for 0.10 nm, having that the dielectric constant of the interfacial SiO
_x
N
_y
layer is higher than that of the SiO
₂
layer. Hence, the interfacial layer consumption is found to be the dominant wearout mode.