Statistical Modeling of Leakage Currents Through SiO2/High-κ Dielectrics Stacks for Non-Volatile Memory Applications

We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO
2
/high-κ dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-κ’s traps on leakage current distribution for Flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-κ tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-κ tunnel stacks and to improve technologyreliability issues related to Flash memory applications.