A merged MuGFET and planar SOI process

Tri-gate MuGFET (Multi-Gate FET) offers advantages compared to bulk silicon, with respect to circuit design, but also has some potential drawbacks in thermal effects and width quantization. An advantage of MuGFET is that with the same processing it is possible to make planar SOI structures, which, depending upon the active silicon thickness, may be fully or partially depleted. This work investigates circuit operation on a merged MuGFET and planar SOI process.