A chip-level modeling approach for rail span collapse and survivability analyses

A general semiautomated analysis technique has been developed for analyzing rail span collapse and survivability of VLSI microcircuits in high-ionizing-dose-rate radiation environments. Hierarchical macrocell modeling permits analyses at the chip level, and interactive graphical postprocessing provides a rapid visualization of voltage, current, and power distributions for a 16K CMOS/SOI SRAM (static random-access memory) and a CMOS/SOS 8-bit multiplier. An efficient method to treat memory arrays and a three-dimensional integration technique for computing sapphire photoconduction from the design layout are presented.<
>