A full-custom design of AES SubByte module with signal independent power consumption

A full-custom design of AES SubByte module based on Sense Amplifier Based Logic is proposed in this paper. Power consumption of this design is independent of both value and sequence of data. Therefore this design is resistant to power analysis attack. This design is implemented using SMIC 0.18um CMOS technology. Simulation results show that it can work at the frequency of 83.3MHz, and its total area is about 0.85mm
²
. This design is suitable for application in the hardware implementation of symmetric-key cryptographic devices that have high security demand.