CMOS pulse-modulation circuit implementation of phase-locked loop neural networks

In this paper, we have applied the pulse-modulation circuit technique to implement phase-locked loop (PLL) neural networks proposed by Hoppensteadt and Izhikevich. The PLL neural network is an oscillatory neural network as a model of associative memory, and it is represented as coupled phase oscillators with periodic phase variables and periodic nonlinear interactions. In our circuit implementation, the phase variables and their summation and subtraction are represented by pulse-width modulation (PWM) signals. The interactions are realized by using nonlinear current waveform sampled with pulse-phase modulation (PPM) signals converted from the PWM signals. We have designed an element circuit and simulated two coupled such circuits with SPICE using the TSMC 0.25 μm device parameters. The results demonstrate that the element circuits synchronized with in- and anti-phase depending on coupling strength at different operation frequencies. The element circuit has an advantage in extracting phase difference between the circuits. This will facilitate implementing of learning by arbitrary spike-timing dependent plasticity (STDP) rules using the phase difference.