Power-saving nano-scale DRAMs with an adaptive refreshing clock generator

An adaptive refreshing circuitry design for DRAMs is presented in this work. The proposed refreshing circuitry uses a voltage comparator to monitor the voltage drop caused by the data loss of a memory cell that results from leakage currents in order to dynamically adjust the refreshing period of the memory cell. Besides, a process variation monitor is also included in the proposed design to compensate the process drifting problem. Therefore, the proposed design is insensitive to temperature variations as well as process drifts. The period of the refreshing clock is automatically adjusted to save a great portion of standby power of DRAMs. A 4-Kb DRAM is implemented by a typical 0.13-μm 1P8M digital CMOS process. The post-layout simulation verifies the correctness of the adaptive refreshing cycles generated by the proposed design.