A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS

This paper presents a very low-voltage low-power pipelined ADC with 0.9-V supply voltage in a 90nm CMOS process. A novel switched-RC sampling MDAC is proposed to obtain high linearity under very low-voltage and low-power conditions without significant degradation in speed or causing any reliability problem. Moreover, by eliminating S/H stage, power consumption is reduced considerably. Pipelined stage scaling, dynamic comparator, and amplifier sharing are also utilized to reduce power more significantly. According to HSPICE simulation results, the 10-bit 100MSample/s ADC with 1-V
p-p,diff
input signal in a 90nm CMOS process and 0.9-V supply voltage achieves an SNDR of 59dB and consumes 15.5mW power.