Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology

This paper examines three different flip-flop designs in subthreshold operation. All flip-flops are simulated in a 65 nm and 90 nm process with a supply voltage ranging from 125 mV to 1V. Process variations are examined at different process corners. Successful operations of a PowerPC 603 flip-flop at all process corners with a supply voltage down to 125 mV is shown at 65 nm. The best PDP and EDP numbers of flip-flops design at V
_DD
= 200 mV in this paper are 53.6 aJ and 0.88 yJs, respectively.