Design of Multigigabit-per-Second Transceiver for Band-Limited High-Speed Data Communication Using DC-Free Signaling

This paper presents a 5-Gb/s transceiver for AC-coupled interconnects using de-free signaling based on symbol-rate-carrier offset quadrature phase-shift-keying modulation. A modified Costas loop for the clock and data recovery is also proposed to perform the receiver function. Without the need of an encoding scheme for dc balance, the proposed modulation can be used in high-speed ac-coupled high-speed interconnect systems. The theory and analysis of the proposed dc-free signaling are discussed in this paper. The fully integrated transmitter and the receiver are implemented using a 0.18-mum CMOS technology. Measurement results demonstrate the transmitted 5-Gb/s data can be successfully recovered by the receiver chip after an ac-coupled FR4 printed circuit board transmission line of up to 20 in. The transceiver consumes 200 mW from a 1.8-V power supply.