Enhanced Stress Proximity Technique with Recessed S/D to Improve Device Performance at 45nm and Beyond

A novel low cost technique to improve device performance by enhanced Stress Proximity Technique (eSPT) with Recessed S/D (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. pFET performance with Ion of 520uA/um at Ioff of 1nA/um was achieved with the low cost processes. With optimized eSPT, 15% improvement in ring delay has been demonstrated.