A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS

The outcome of the recent research effort in the design of Ka band and mm-wave silicon ICs has motivated several industrial projects toward the realization of chipsets for broadband communications and automotive cruise control applications. Performance of standard CMOS implementations has proved sufficient up to 60GHz range and examples of operating blocks even beyond 60GHz have been presented [1, 2]. Still, the choice of the receiver architecture entails several peculiar considerations in order to achieve a robust low power solution. Frequency conversion to DC or close to DC has been used in most cases to allow a high level of integration in CMOS. On the other hand, at high frequencies, to save power in both the VCO and dividers, it is desirable to synthesize a reference frequency that is lower than the received frequency. A multiplier, following the synthesizer, can be used but this prevents I/Q downconversion, mandating a further IF-processing stage. Moreover, leakage between signal and LO ports, exacerbated at high frequency, determines offset, inter-modulation distortion and LO re-irradiation, deleterious for example in automotive radars. We propose a half harmonic 24GHz direct-conversion I/Q-receiver front-end with integrated multi-phase LO generation in 65nm CMOS. Experiments show that adequate performance is achieved in a compact (2.1mm2) low-power (below 100mW) solution in an ultrascaled CMOS process.