A CMOS Image Sensor Integrating Column-Parallel Cyclic ADCs with On-Chip Digital Error Correction Circuits

This paper presents a CMOS image sensor integrating a 14b column-parallel cyclic ADC with on-chip digital error correction circuits. Column-parallel ADC arrays are located both above and below the pixel array. The area of the on-chip error-correction logic including memories for all the error coefficients of the 640 ADC channels is 0.85mmx7.9mm.