Microstrip Mismatching Technique for Reducing SSN in High Speed Integrated Circuit

In CMOS circuits, where consumption is not steady, current peaks produce voltage drops through the inductance, which manifest themselves as fluctuations in the internal supply voltages. This kind of noise is known as delta-I noise, simultaneous switching noise (SSN) or ground bounce. This paper describes a novel method to reduce the SSN: on-chip microstrip mismatching technique in the power supply wire. The microstrip is connected with the bonding wire. The microstrip is embedded in Si dielectric upon Si substrate and does not increase the size of the chip. Not only the impedance mismatching technique between the bonding wire and the microstrip is considered in order to get source reflection coefficient |Gamma
g
| = 1 at the end source, but also the microstrip length is properly designed to get source reflection coefficient Gamma
_gout
= -1 at the end microstrip and make the input impedance of the microstrip looking out from the CMOS unit at nodes p and n close to zero, thereby shortening out the noise voltage. Si has high dielectric constant and can also greatly attenuate the noise because of high dielectric loss. The results of
S

₂₁
depicts that the transmission coefficient is around -40 dB and the noisy power produced by the bonding wire can not be delivered. The technique developed in this paper has the advantage of simplicity, easy realization, non-oscillation and there is no size, weight, and power dissipation penalties.