An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept

In this paper, we present an FPGA prototype implementation of a rotator-on-chip (RoC), a simple and scalable novel network-on-chip (NoC) based on the token-ring concept. The reported prototype design is generic with respect to the number of nodes and data channels. We report synthesis results showing a O(N log N) area complexity, where N represents the number of nodes, with a quasi-linear aggregate bandwidth growth. The slice utilization is less than 25% on a Xilinx VP100 for a 32 nodes version of the RoC, supporting an aggregate bandwidth of about 12 GB/s. Moreover, the number of channels can be easily configured to trade-off area versus performance. These configurations have been validated by simulation and implemented on a FPGA development board.