High-Performance Low-Power Digital Linear Interpolation Filter

A new technique to implement digital interpolation filter is presented in this paper. The technique employs a sample calculation functional block which reduces the hardware required to realize the filter by orders of magnitude. The filter is realized with 80×160 μm
²
using 65 nm CMOS technology. Over Sampling Rate of up to 256 is achieved for 16-bit digital data sampled at 705,600 bps. The filter dissipates 77.68 mW when operating at frequency of 833.3 MHz.