A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 $\mu{\hbox{m}}$ CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 ${\hbox{mm}}^2$. The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 2$^{7} -$1 PRBS. The measured bit error rate for a 10 Gb/s 2$^{7} -$ 1 PRBS is less than 10 $^{-12}$.