Electrical Properties of Low-$V_{T}$ Metal-Gated n-MOSFETs Using $\hbox{La}_{2}\hbox{O}_{3}/\hbox{SiO}_{x}$ as Interfacial Layer Between HfLaO High- $\kappa$ Dielectrics and Si Channel

In this letter, we report that by employing the $\hbox{La}_{2}\hbox{O}_{3}/ \hbox{SiO}_{x}$ interfacial layer between HfLaO $(\hbox{La} = \hbox{10}\%)$ high-$\kappa$ and Si channel, the $\hbox{Ta}_{2}\hbox{C}$ metal-gated n-MOSFETs $V_{T}$ can be significantly reduced by $\sim$350 mV to 0.2 V, satisfying the low- $V_{T}$ device requirement. The resultant n-MOSFETs also exhibit an ultrathin equivalent oxide thickness ( $\sim$1.18 nm) with a low gate leakage ( $J_{G} = \hbox{10}\ \hbox{mA/cm}^{2}$ at 1.1 V), good drive performance ($I_{\rm on} = \hbox{900}\ \mu\hbox{A}/\mu\hbox{m}$ at $I_{\rm soff} = \hbox{70}\ \hbox{nA}/\mu\hbox{m}$), and acceptable positive-bias-temperature-instability reliability.