A 0.9-V 10-bit 100-MSample/s pipelined ADC using switched-RC and opamp sharing techniques

This paper presents a very low-voltage low-power pipelined ADC with 0.9-V supply voltage in a 90 nm CMOS process. A novel switched-RC sampling MDAC is used to obtain high linearity under low-voltage condition without significant degradation in speed. With the aim of achieving low-voltage and low-power operation, a non-uniform per-stage resolution which increases the resolution of the back-end stages at the architectural level, and an opamp sharing technique at the circuit level are used. According to HSPICE simulation results, the 10-bit 100 MSample/s ADC with 1-V
_p.p,diff
input signal in a 90 nm CMOS process and 0.9-V supply voltage achieves an SNDR of 58 dB and consumes 17.6 mW power.