A relocation method for circuit modifications

For the placement of VLSI, the migration problem becomes important. In this paper, we propose a novel migration method. In this method, the resultant placement keeps the structure of the original placement, called model placement, as same as possible. For the purpose, we minimize the sum of the area difference between the model placement and the relocated one and the total amount of displacement between them. Moreover, to archive a short run-time, we employ the limitation of solution space and the change of packing origin in the optimization process. We construct the system on Sequence-Pair. Experimental results show that our approach preserves the chip area and the overall circuit structure with 98% less run-time than that by a naive Simulated Annealing.