Fault tolerance of feed-forward artificial neural network architectures targeting nano-scale implementations

Several circuit architectures have been proposed to overcome logic faults due to the high defect densities that are expected to be encountered in the first generations of nanoelectronic systems. How feed-forward artificial neural networks can possibly be exploited for the purpose of conceiving highly reliable Boolean gates is the topic of this paper. Computer simulations show that feed-forward artificial neural networks can be trained to absorb faults while implementing Boolean functions of various complexity. Using this approach, it can be shown that very high device failure rates (up to 20%) can be accommodated. The cost is to be paid in terms of hardware overhead, which is comparable to the area cost of conventional hardware redundancy measures.