Optimized realization of large-size two’s complement multipliers on FPGAs

This paper presents an optimized design approach of two’s complement large-size multipliers using embedded multipliers in FPGAs. The realization is based on Baugh-Wooley’s algorithm. To achieve efficient implementation, a set of optimized schemes for the realization of the addition of partial products is proposed. The implementations of the multipliers have been carried out for operands with sizes from 20 to 128 bits. The results indicate that our proposed approach outperforms the traditional methods by as high as 50% in terms of LUT-delay product.