A systolic array for sequence comparison based on two-logic-levels processing element

In this work, we implement a Dynamic Programming (DP) algorithm for Sequence Comparison (SC) purposes. We aimed at obtaining a better compromise between the processing acceleration optimization and the hardware cost. A simplified Edit Distance (ED) calculation formula is used, where we introduce two new simplified logical equations based on this last formula. A Systolic Array (SA) based on our simplified Processing Element (PE) can compare sequences with a great length and a high processing frequency. Our system speed-up shows a gain varying between 13% and 142% compared to other systems, according to the considered FPGA family.