Decimation filter for a low-power sensor-interface system

The presented decimator was designed to decimate a delta- sigma A/D-converter as part of a sensor-interface system for a three axis accelerometer. The sensor-interface system is designed with a very low power consumption target so the main design target for the decimator is also power consumption. Further, the area of the decimator part was a constraint limiting the design. The decimator uses three parallel filters for the x-, y- and z-axes, 12-bit output accuracy is used for each channel. The downsampling ratio is programmable and can be 16, 32, 64 ... 1024. All the 12-bit wide outputs from the 3 filters are fed to a parallel-to- serial converter that outputs the 36 bits in a serial form. The design was implemented with a 0.25 mum process as part of the sensor interface system chip, the area for the decimator was 0.259 mm
²
. Measured power consumption of decimator is between 0.1 muW and 5 muW depending on the used operation mode and voltage.