A 2 μm Stacked CMOS 64K SRAM

The demands for high density and high performance static RAMs have been increasing ever since their introduction about a decade back. The future of SRAM development, however, is strongly coupled with the resolution of a key issue, namely, the 6-T memory cell. The poly load cell, although small, is prone to soft errors and has inherent performance marginalities. On the other hand a full CMOS cell has better performance but is twice as large as the poly load cell. This paper will describe an asynchronous 8K x 8 static RAM that utilizes a stacked 6-T CMOS cel(4). At 307 um2 it is comparable in size to a poly load cell, however its performance is similar to that of the bulk CMOS 6-T cell. The load current of the poly transistor is about a factor of 100 smaller than the bulk P-Channel device and about five orders of magnitude larger than the poly resistor load (Fig.1). This load device characteristics and the cell immunity to latch-up make it a very attractive alternative for the next generation of SRAMs. The focus of this work is on the performance of the cell in the memory circuit environment rather than on the external features of the memory chip.