An Improved Fabrication Process for Multi-Level Polysilicon Structures

Doped polysilicon layers are extensively used as a gate material or as an interconnect in silicon MOS VLSI circuits. Commonly, the polysilicon layers are deposited by LPCVD at temperatures of approximately 620'C, and electrical isolation is provided by SiO2 thermally-grown from the underlying polysilicon. It is well known that oxides grown from polysilicon (polyoxides) have a lower dielectric strength and exhibit enhanced Fowler-Nordheim (F-N) tunneling current for a given applied field compared to SiO2 grown from mono-crystalline, bulk silicon [1]. These effects have been attributed to non-uniformities in the SiO2 film thickness [2), and to the texture (surface roughness) of the polysilicon/SiO2 interface which leads to localized electric fields being much greater than the average applied field [3]. The surface roughness of the polysilicon film can be affected by deposition temperature and annealing, the doping technique used, enhanced oxidation at grain boundaries, grain growth mechanisms, and the oxidation ambient and temperature [3-7].