Walled Collector Oxide Isolated I2L

A combination of high performance linear and logic functions coupled with very dense low power logic are very desirable features for a VLSI technology. Bipolar technology can produce very high speed ECL logic coupled with an excellent linear capability. However, high density low power logic is not easily achieved. Circuits employing I2L processes have demonstrated good high speed performance (1,2) at the expense of complex processing and lack of analogue compatibility. This paper discussed a technique which achieves good I2L performance on an oxide isolated bipolar process without compromising good linear and ECL circuit performance. A combination of a novel gate configuration and a modest process modification is used.