Limits to Scaling MOS Devices

Over the past few years, MOS devices have been scaled systematically to achieve high performance and high density. This involved scaling down lateral and vertical dimensions (1) reducing the supply voltage and adjusting the substrate doping to achieve appropriate threshold voltages and to inhibit punch through effects. However, as devices are scaled down, physical and technological parameters play an increasingly important role in limiting the gains otherwise achievable. Among the more important factors are: