A Mo Gate Submicron MOS Process Using Optical Projection Lithography

There is a great deal of interest in using optical projection lithography (OPL) for submicron VLSI because of its established utility and experience base, and its relatively low capital cost compared to other advanced lithographies. In order to develop NMOS and PIOS device design for CMOS, we have established submicron NMOS and PMOS processes which exclusively employ OPL. The gate material is Mo, which is especially useful for CIIOS because of the value of its work function. In this report, results from the submicron MIOS process development are presented. We have fabricated circuits with designed feature size as small as 0.6 μm, and devices with gate length as short as 0.5 μm using conventional optical tools. In particular, we have fabricated NMOS ring oscillators with propagation delay time per stage as fast as 30 ps.