Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies

Dual-threshold-voltage (V
_T
) CMOS is an effective way to reduce leakage power in high-performance very-large-scale-integration circuits. In this paper, we explore the technology design space for dual-threshold-voltage transistor design in deep-sub-100-nm technology nodes. We propose a technique of achieving high-V
_T
(HVT) devices using thicker gate-sidewall offset spacers to increase the channel length without increasing the printed-gate length. The effectiveness of all the dual-V
_T
technology options-increasing channel doping, increasing gate length, and proposed technique of increasing spacer thickness-is analyzed at transistor and basic logic gate level. Results on 65-nm partially depleted silicon-on-insulator and double-gate technologies indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body-doping devices. Our proposed technique, however, incurs extra fabrication mask similar to achieving HVT by increasing body doping.