Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${\hbox{Pr}}_{2}{\hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr
₂
O
₃
as gate dielectric is investigated for the first time. Using the Pr
₂
O
₃
gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr
₂
O
₃
/poly-Si interface to improve the device electrical properties. The Pr
₂
O
₃
TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr
₂
O
₃
TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr
₂
O
₃
TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr
₂
O
₃
TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.