Performance evaluation of VHDL coding techniques for optimized implementation of IEEE 802.3 transmitter

This paper is focus on to implement IEEE 802.3 MAC transmitter using different VHDL coding techniques. We propose consequences of VHDL coding styles on area utilization and speed. Optimization for maximum speed can be achieved by FSM based approach. While targeting higher speed device area utilization is severely affected. To have a balance among area and speed optimization, we have explored synthesis options along with VHDL coding styles. With this approach FPGA area utilization for MAC implementation is reduced. Recognizing the importance of hardware architecture in relation to optimization of area and speed of operation, our implementation results shows that the performance depends on area constraint, speed constraint , vhdl coding style, FSM encoding styles, multiplexer , priority encoder extraction, fan out and register balancing.