Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$\kappa$ Gate Dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO
₂
and HfSiO
_x
, high-k gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-k gate dielectrics exhibited superior device performance in terms of higher I
_on
/I
_off
current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V
_th
), relative to conventional deposited-SiO
₂
, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO
_x
, as the gate dielectric had ca. 1.73 times the mobility (mu
_FE
) relative to that of the deposited-SiO
₂
TFTs; in contrast, the HfO
₂
TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO
₂
TFTs. The immunity of the HfSiO
_x
, TFTs was better than that of the HfO
₂
TFTs-in terms of their V
_th
shift, SS degradation, mu
_FE
degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiO
_x
, rather than HfO
₂
, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.