High Speed I/O Design Optimization in FCMMAP Packaging

This paper presents the design optimization work and its implementation in Intel's High Speed Telecommunication and Optical products in the Flip-Chip Molded-Matrix Array Package (FCMMAP) packaging. The overall high speed modeling methodologies will be explained in this paper to describe electrical analysis work needed to identify the optimizations in the design. Specific substrate design attributes such as impedance matching, discontinuity and material losses will be presented. Validation results based on Intel's first high speed 40 Gbps prototype will be published in this paper as well.