High-Performance Polysilicon TFTs Using Stacked $ \hbox{Pr}_{2}\hbox{O}_{3}$/Oxynitride Gate Dielectric

In this letter, we have developed, for the first time, a stacked Pr
₂
O
₃
/SiO
_x
N
_y
gate dielectric into low-temperature polysilicon (poly-Si) thin-film transistors (TFTs). A high- performance TFT device that has a high effective carrier mobility, a high driving current, a small subthreshold swing, and a high I
_ON
/I
_OFF
current ratio can be achieved. This phenomenon is attributed to the smooth Pr
₂
O
₃
/poly-Si interface provided by the N
₂
O plasma treatment. The presence of the SiO
_x
N
_y
buffer layer also enhanced the electrical reliability of the Pr
₂
O
₃
poly-Si TFT. All of these results suggest that a high-k Pr
₂
O
₃
gate dielectric prepared under the buffer layer is a good candidate for high- performance TFTs.