On-Chip Power-Grid Simulation Using Latency Insertion Method

Ensuring the integrity of the power supply in the power distribution networks (PDNs) of a chip is essential for building reliable high-performance chips. To ensure the power integrity, accurate, and memory- and time-efficient simulation approaches for simulating the power-supply noise in the on-chip PDN are essential. In this paper, a finite-difference formulation based on the latency insertion method (LIM) has been employed for simulating the power-supply noise in the on-chip PDN. A new common-mode type equivalent circuit has been proposed. In this equivalent circuit, a capacitance to ideal ground may not be present at all the nodes. Further, the nodes can be capacitively coupled to each other. To avoid inverting a large nonbanded matrix, a small capacitance to ground is added to a node that did not have any capacitance to ground, and a small series inductance is added to any floating capacitor that did not have any series inductance. Approximate closed-form expressions to compute the values of these capacitances to ground and series inductances have been proposed. The accuracy of the LIM-enabled transient simulation and the accuracy of the proposed closed-form expressions have been demonstrated. The memory and time complexity of the simulation for each time step have been shown to be O(N
_n
) each, where N
_n
is the number of nodes in the equivalent circuit. Stability condition is derived for the first time for multidimensional inhomogeneous RLC circuit. A upper bound of the time step is derived from the stability condition. Using this bound on the time step, the runtime of the overall transient simulation has been estimated to be approximately proportional to N
_n

^2-2.5
for N
_n
in the order of millions.