Optimization of thick resist in 90nm mirror- bit® flash memory to improve sector edge cell threshold voltage

In this paper, we describe the characterization and optimization of thick resist in 90nm flash memory processing to improve sector-edge cell threshold voltage (Vt) uniformity. It was observed that upon high-energy implantation, edge footing of thick resist increased sufficiently to allow some possible unintentional dopant penetration into sector WL regions, lowering sector edge Vt. Careful characterization and optimization of thick resist, coupled with layout modification, was successful in eliminating low sector-edge Vt and improving Vt uniformity by up to 20%.