A Coarse Grained Reconfigurable Architecture for Variable Block Size Motion Estimation

This paper proposes a novel application-specific coarsegrained reconfigurable architecture with a flexible network on chip (NoC) mechanism. This architecture supports variable block size motion estimation (VBSME) with much less resources than other architectures. The intelligent NoC router supports full search motion estimation algorithm as well as other fast search algorithms like diamond and hexagonal search. Our model is a hierarchical hybrid processing element based 2D architecture which supports reuse of search data between the processing elements with the help of NoC routers. Results show that the area occupied by the proposed architecture is about one-seventh of the area occupied by the state of the art ASIC implementation with comparable operational frequency to sustain 30fps.