A 1.5dB NF, 5.8GHz CMOS low-noise amplifier with on-chip matching

In this paper we describe the design of an integrated 5.8 GIU low noise amplifier in 90 nm CMOS technology. The design is a tuned cascode LNA with on-chip matching that has a sufficiently low noise figure and high gain to enable high receiver sensitivity. The measured performance is NF=l.SdB, gain=28 dB, IIP3= -5 dBm and Pd=15m\V; and NfW.SdB, gain=23 dB, HP3=-17 dBm and Pd=8 m\V.