Strained Si n-FET featuring compliant SiGe Stress Transfer Layer (STL) and Si0.98C0.02 source/drain stressors for performance enhancement

We report the first demonstration of an n-channel transistor (n-FET) featuring a compliant Si
_0.75
Ge
_0.25
stress transfer layer (STL) and in situ doped Si
_0.98
C
_0.02
source/drain (S/D) stressors for performance enhancement. Due to the stress coupling between Si
_0.98
C
_0.02
and the compliant SiGe STL, additional strain is imparted to the Si channel. Devices with gate length LG down to 30 nm were fabricated. The enhanced strain effects resulted in 65% drive current improvement in strained n-FETs over control n-FETs for a given DIBL of 0.20 V/V.